1. Field of the Invention
The present invention relates to testing of integrated circuits, and more particularly to a method for correlating test results of an integrated circuit die across various stages of the manufacturing process.
2. Description of the Related Art
Improvements in semiconductor processes are making possible integrated circuits of increasing size and complexity. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems, including memories, can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as xe2x80x9cdiexe2x80x9d or xe2x80x9cchipsxe2x80x9d) may use many functions that previously could not be implemented on a single die. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, due to the complex nature of today""s integrated circuits and a concomitant sensitivity to variations in manufacturing processes, manufacturers are constantly confronted with new testing challenges.
Before manufacturers release integrated circuits for shipment, the devices typically undergo a variety of testing procedures. In ASIC devices incorporating integrated memories, for example, specific tests are performed to verify that each of the memory cells within the integrated memory array(s) is functioning properly. This testing is necessary because perfect yields are difficult to achieve. It is not uncommon for a certain percentage of unpackaged ASIC die to contain memory cells which fail testing processes, due largely to non-systemic manufacturing defects and degradation faults. Such manufacturing issues are likely to increase as process geometries continue to shrink and the density of memory cells increases. Even today, up to 100 Mbits or more of dynamic random access memory (DRAM), or several megabits of static random access memory (SRAM) or flash memory can be integrated onto a single integrated circuit.
A number of ASIC memory testing strategies have evolved, many of which involve use of an external memory tester or Automated Test Equipment (ATE). If memory is accessible from input/output (I/O) pins, either directly or by multiplexing, a hardware test mode can be utilized. In this mode, a production test system accesses the memory directly by writing to and reading from the memory bits. While this methodology does not use any chip area other than simple multiplexing circuitry, it is limited to on-chip memories and other circuitry accessible via I/O pins. Another drawback of this approach is that ATE capabilities are generally not available to end-users once the devices have been shipped, making it difficult to detect faults occurring after shipment.
If an embedded memory is buried deeply within an ASIC, built-in self-test (BIST) is often considered the most practical and efficient test methodology and is becoming increasing popular with semiconductor vendors. BIST allows timely testing of the memory with a reasonably high degree of fault coverage, without requiring complex external test equipment and large amounts of external access circuitry. One advantage BIST has over many traditional testing methods is that with BIST, memory or logic circuitry can be tested at any time in the field. This capability offers some degree of continued fault protection.
BIST refers in general to any test technique in which test vectors are generated internal to an integrated circuit or ASIC. Test vectors are sequences of signals that are applied to integrated circuitry to determine if the integrated circuitry is performing as designed. BIST can be used to test memories located anywhere on the ASIC without requiring dedicated I/O pins, and can be used to test memory or logic circuitry every time power is applied to the ASIC, thereby allowing an ASIC to be easily tested after it has been incorporated in an end product. A number of software tools exist for automatically generating BIST circuitry, including RAMBIST Builder by LSI Logic of Milpitas, Calif. Such software produces area-efficient BIST circuitry for testing memories, and reduces time-to-market and test development costs.
In the BIST approach, a test pattern generator and test response analyzer are incorporated directly into the device to be tested. BIST operation is controlled by supplying an external clock and via use of a simple commencement protocol. BIST test results are typically compressedxe2x80x94usually to the level of xe2x80x9cpassedxe2x80x9d or xe2x80x9cfailedxe2x80x9d. At the end of a typical structured BIST test, or xe2x80x9crunxe2x80x9d, a simple pass/fail signal is asserted, indicating whether the device passed or failed the test. Intermediate pass/fail signals may also be provided, allowing individual memory locations or group of locations to be analyzed. Unlike external testing approaches, at-speed testing with BIST is readily achieved. BIST also alleviates the need for long and convoluted test vectors and may function as a surrogate for functional testing or scan testing. Further, since the BIST structures exist and remain active throughout the life of the device, BIST can be employed at the board or system level to yield reduced system testing costs, and to reduce field diagnosis and repair costs.
In addition to the aforementioned testing procedures, manufacturers use a number of techniques to repair faulty memories when feasible. Such techniques include bypassing defective cells using laser procedures and fused links that cause address redirection. However, such techniques are limited to one-time repair and require significant capital investment. Further, these techniques may leave integrated circuits useless if the repaired memories become defective after shipment from the manufacturing sitexe2x80x94even where test equipment is available to end users, traditional field repairs have been expensive, time consuming, and largely impracticable.
In order to enhance the repair process, on-chip built-in self repair (BISR) circuitry for repairing faulty memory cells has evolved. BISR circuitry functions internal to the integrated circuit without detailed interaction with external test or repair equipment. In the BISR approach, suitable test algorithms are preferably developed and implemented in BIST or BIST-like circuitry. These test patterns may be capable of detecting stuck-at, stuck-open, bridging faults and retention faults during memory tests. Following execution of the test patterns, the BISR circuitry analyzes the BIST xe2x80x9csignaturexe2x80x9d (results) and, in the event of detected faults, automatically reconfigures the defective memory utilizing redundant memory elements to replace the defective ones. A memory incorporating BISR is therefore defect-tolerant. The assignee of the present invention, LSI Logic Corporation, has addressed different methods of repairing faulty memory locations utilizing BIST and BISR circuitry, as disclosed in U.S. Pat. No. 5,764,878, entitled xe2x80x9cBUILT-IN SELF REPAIR SYSTEM FOR EMBEDDED MEMORIESxe2x80x9d, and U.S. patent application Ser. No. 08/970,030, now abandoned entitled xe2x80x9cMETHOD FOR SEPARATING PRIME AND REPAIRED INTEGRATED CIRCUITS INCORPORATING BUILT-IN SELF TEST AND BUILT-IN SELF REPAIR CIRCUITRY,xe2x80x9d both of which are hereby incorporated by reference as if set forth in their entirety.
BISR compliments BIST because it takes advantage of on-chip processing capabilities to re-route bad memory bits rather than using an expensive and slow laser burning process to replace faulty memory locations. Some BISR circuitry is capable of repairing the faulty memory locations by redirecting the original address locations of faulty memory lines to the mapped addressed locations of the redundant columns and rows. Options for repair include either row and column replacement when a faulty bit is found in a particular row or column.
During the testing process, it is often desirable to separate so-called xe2x80x9cprime diexe2x80x9d (integrated circuit die in which no redundant BISR memory components were utilized during initial testing) from xe2x80x9crepaired diexe2x80x9d. Separating integrated circuit die in this manner provides an indication of quality and fault tolerance. Because the BIST and BISR circuitry of an integrated circuit continue to be functional in the field, any BISR redundancy resources not expended during initial testing are available to repair faults that may occur in the field. Consequently, prime die have a higher degree of fault tolerance, and can often be sold by manufacturers for a premium.
An important feature of any integrated circuit is its reliability. Engineers strive to design integrated circuits that operate under a range of conditions (including temperatures and voltages) without malfunctioning. Therefore, it is often desirable to test dies (or xe2x80x9cdicexe2x80x9d) under realistic field conditions during the manufacturing production cycle to ensure operability. This testing is done before singulation (i.e., separation) of the individual dies from a wafer. Furthermore, instead of using costly external test patterns to test memory locations, it is desirable to use the BIST circuitry with external ATE. The external tester is programmed to xe2x80x9ctestxe2x80x9d a die""s embedded memory by examining the outputs of the its BIST circuitry. With stand alone memory devices, manufacturers use dedicated memory ATEs to test over a range of conditions. Typically, a worst set of operating conditions is applied and any detected faults, if possible, are repaired using fuse structures. This approach may not work for integrated circuits incorporating embedded memories and BIST/BISR capabilities, as test and repair routines are generally executed only at power-up.
Running current BIST algorithms may not adequately detect memory locations having faults that are dependent on operating conditions. Even with BIST/BISR, memory elements can pass power-up BIST under one set of conditions, only to fail during normal operation when the die is subsequently subjected to another set of conditions. Since BIST/BISR is typically run only once during a power cycle, any memory locations that fail after power-up may not be repaired. Such failures may cause the chip to be unsuitable for its intended use.
Prior test methods may fail to introduce realistic field conditions or stress factors (e.g., normal variation in voltage, timing, power supply disturbances and temperature) during these tests to insure adequate fault coverage. Consequently, suspect memory locations that pass under an initial set of operating conditions but fail under a subsequent set of operating conditions may not be identified by current production test programs. Further, since BISR structures have a limited number of redundant memory locations, a device may be repairable only under select operating conditions. The problem may be exacerbated by the rigors of the packaging process, which may give rise to failure mechanisms not present in a given integrated circuit before singulation.
Currently, no satisfactory method exists for correlating memory test results (such as BIST test results) across the various stages of the manufacturing and packaging processes for integrated circuits. Such test results may include, for example, wafer-level testing of the integrated circuit and test results from corresponding packaged devices.
Briefly, the present invention provides a method for improving the fault coverage of manufacturing tests for integrated circuits having structures such as embedded memories. An identification circuit is provided to allow for comparison of failure mechanisms at different stages of the manufacturing process.
In the disclosed embodiment of the invention, the integrated circuit die of a semiconductor wafer are provided with a fuse array or other circuitry capable of storing an identification number, an embedded memory or similar circuit, and BIST/BISR circuitry. At a point early in the manufacturing test process, the fuse array of each integrated circuit die is encoded with an identification number to differentiate the die from other die of the wafer or wafer lot. Preferably, the identification numbers are capable of being read by ATE. The integrity of the embedded memory of each integrated circuit die is then tested under a variety of conditions (also referred to as stress factors) via the BIST and BISR circuitry. The results of these tests are stored in ATE and associated with a particular integrated circuit die via the identification number of the die. At each manufacturing test step of a method according to the disclosed embodiment of the invention, the fuse identification numbers are read into the test database along with the BIST signature or memory repair solution to facilitate failure analysis. The test results for the pre-packed integrated circuit die can be compared for a variety of test conditions to determine if the functionality of the device is questionable and, if so, the device is discarded.
The integrated circuit die are next singulated and packaged. Under other test approaches, the identification of the integrated circuit die (e.g., the x-y coordinates of the individual die of the wafer) are lost following singulation. The fuse identification circuit of the present invention, however, allows prior test results to be correlated with test results of the packaged part.
Accordingly, the manufacturing test process then continues for the packaged integrated circuits. As with the unsingulated die, the packaged parts are subjected to one or more sets of stress factors, with data being gathered at each stage. Again, test results (e.g., faulty memory locations as determined by the BIST circuitry) are correlated to specific parts via the identification number of the integrated circuit die. The test results of the various stages are next compared to determine if any detected repairable failures are uniform across the various operating conditions. In general, the assumption is made that an integrated circuit IC that exhibits different failure mechanisms at different stages of the testing/manufacturing process is questionable and the part is discarded.
This novel methodology of redundancy analysis allows circuits with self-repair capabilities (such as embedded memories) to be tested at various stages of the manufacturing process using a standard logic tester and permits detection of likely field errors that are dependent on operating conditions, thereby improving fault coverage and increasing the quality of the end product.